CLK:IN STD_LOGIC;
CLK1:IN STD_LOGIC;
UP0:OUT STD_LOGIC;
DOWN0:OUT STD_LOGIC);
END KEY;
ARCHITECTURE ONE OF KEY IS
SIGNAL UPT1,UPT2,UPT3,DOWNT1,DOWNT2,DOWNT3:STD_LOGIC;
BEGIN
PROCESS (CLK1)
BEGIN
if(CLK1'EVENT AND CLK1='1') THEN
UPT1<=UP;
UPT2<= UPT1;
DOWNT1<=DOWN;
DOWNT2<=DOWNT1;
END IF;
END PROCESS;
UPT3 <=NOT UPT2;
DOWNT3 <=NOT DOWNT2;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN
UP0 <=CLK1 AND UPT
100万分频器模块设计-571字.pdf